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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
8-Bit Serial-Input/ Parallel-Output Shift Register
High-Performance Silicon-Gate CMOS
The MC54/74HC164A is identical in pinout to the LS164. The device inputs are compatible with standard CMOS outputs; with pullup resistors, they are compatible with LSTTL outputs. The MC54/74HC164A is an 8-bit, serial-input to parallel-output shift register. Two serial data inputs, A1 and A2, are provided so that one input may be used as a data enable. Data is entered on each rising edge of the clock. The active-low asynchronous Reset overrides the Clock and Serial Data inputs. * * * * * * Output Drive Capability: 10 LSTTL Loads Outputs Directly Interface to CMOS, NMOS, and TTL Operating Voltage Range: 2 to 6 V Low Input Current: 1 A High Noise Immunity Characteristic of CMOS Devices In Compliance with the Requirements Defined by JEDEC Standard No. 7A * Chip Complexity: 244 FETs or 61 Equivalent Gates LOGIC DIAGRAM
SERIAL DATA INPUTS 1 2 DATA
MC54/74HC164A
J SUFFIX CERAMIC PACKAGE CASE 632-08
1
14
14 1
N SUFFIX PLASTIC PACKAGE CASE 646-06
14 1
D SUFFIX SOIC PACKAGE CASE 751A-03
14 1
DT SUFFIX TSSOP PACKAGE CASE 948G-01
ORDERING INFORMATION MC54HCXXXAJ MC74HCXXXAN MC74HCXXXAD MC74HCXXXADT Ceramic Plastic SOIC TSSOP
A1 A2
3 4 5 6 10 11 12 CLOCK 8 13
QA QB QC QD QE QF QG QH PARALLEL DATA OUTPUTS
PIN ASSIGNMENT
A1 A2 QA QB QC 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VCC QH QG QF QE RESET CLOCK
RESET
9
PIN 14 = VCC PIN 7 = GND
QD GND
FUNCTION TABLE
Inputs Outputs Reset Clock A1 A2 QA QB ... QH L X X X L L...L H X X No Change H H D D QAn ... QGn H D H D QAn ... QGn D = data input QAn - QGn = data shifted from the preceding stage on a rising edge at the clock input.
3/96
(c) Motorola, Inc. 1996
3-1
REV 0
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* Maximum Ratings are those values beyond which damage to the device may occur. Functional operation should be restricted to the Recommended Operating Conditions. Derating -- Plastic DIP: - 10 mW/_C from 65_ to 125_C Ceramic DIP: - 10 mW/_C from 100_ to 125_C SOIC Package: - 7 mW/_C from 65_ to 125_C TSSOP Package: - 6.1 mW/_C from 65_ to 125_C For high frequency or heavy load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
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MAXIMUM RATINGS*
MOTOROLA
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
RECOMMENDED OPERATING CONDITIONS
MC54/74HC164A
Symbol
Vin, Vout
Symbol
Symbol
VCC
Vout
Tstg
ICC
Iout
VCC
Vin
PD
TL
VOH
tr, tf
Iin
TA
VIH
VIL
Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP, SOIC or TSSOP Package) (Ceramic DIP)
Storage Temperature
Power Dissipation in Still Air, Plastic or Ceramic DIP SOIC Package TSSOP Package
DC Supply Current, VCC and GND Pins
DC Output Current, per Pin
DC Input Current, per Pin
DC Output Voltage (Referenced to GND)
DC Input Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Input Rise and Fall Time (Figure 1)
Operating Temperature, All Package Types
DC Input Voltage, Output Voltage (Referenced to GND)
DC Supply Voltage (Referenced to GND)
Minimum High-Level Output Voltage
Maximum Low-Level Input Voltage
Minimum High-Level Input Voltage
Parameter
Parameter
Parameter
Vin = VIH or VIL |Iout| 20 A
Vin = VIH or VIL |Iout| |Iout| |Iout|
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
Vout = 0.1 V or VCC - 0.1 V |Iout| 20 A
v
v
v
VCC = 2.0 V VCC = 4.5 V VCC = 6.0 V
Test Conditions
- 0.5 to VCC + 0.5
- 0.5 to VCC + 0.5
3-2 - 65 to + 150 - 0.5 to + 7.0 - 55 Min 2.0 Value
v 2.4 mA v 4.0 mA v 5.2 mA
0 0 0
0
50
25
20
260 300
750 500 450
+ 125
1000 500 400
VCC
Max
6.0
VCC V
3.0 4.5 6.0
2.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
Unit
Unit
mW
mA
mA
mA
_C
_C
_C
ns
V
V
V
V
V
-55_C to 25_C
0.5 0.9 1.35 1.8
1.5 2.1 3.15 4.2
2.48 3.98 5.48
1.9 4.4 5.9
This device contains protection circuitry to guard against damage due to high static voltages or electric fields. However, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high-impedance circuit. For proper operation, Vin and Vout should be constrained to the range GND (Vin or Vout) VCC. Unused inputs must always be tied to an appropriate logic voltage level (e.g., either GND or VCC). Unused outputs must be left open.
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 0.5 0.9 1.35 1.8 1.5 2.1 3.15 4.2 2.34 3.84 5.34 1.9 4.4 5.9
v
0.5 0.9 1.35 1.8
1.5 2.1 3.15 4.2
2.20 3.70 5.20 1.9 4.4 5.9
v
Unit
V V V
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NOTES: 1. For propagation delays with loads other than 50 pF, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). 2. Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D). NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
High-Speed CMOS Logic Data DL129 -- Rev 6 Symbol Symbol tPLH, tPHL tTLH, tTHL VOL tPHL fmax CPD ICC Cin Iin Maximum Quiescent Supply Current (per Package) Maximum Input Leakage Current Maximum Low-Level Output Voltage Power Dissipation Capacitance (Per Package)* Maximum Input Capacitance Maximum Output Transition Time, Any Output (Figures 1 and 4) Maximum Propagation Delay, Reset to Q (Figures 2 and 4) Maximum Propagation Delay, Clock to Q (Figures 1 and 4) Maximum Clock Frequency (50% Duty Cycle) (Figures 1 and 4) Parameter Parameter Vin = VIH or VIL |Iout| 20 A Vin = VCC or GND Iout = 0 A Vin = VCC or GND
* Used to determine the no-load dynamic power consumption: PD = CPD VCC 2 f + ICC VCC . For load considerations, see Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
AC ELECTRICAL CHARACTERISTICS (CL = 50 pF, Input tr = tf = 6 ns)
DC ELECTRICAL CHARACTERISTICS (Voltages Referenced to GND)
Vin = VIH or VIL |Iout| |Iout| |Iout|
v
Test Conditions
3-3
v 2.4 mA v 4.0 mA v 5.2 mA
VCC V
VCC V
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
2.0 3.0 4.5 6.0
6.0
6.0
3.0 4.5 6.0
2.0 4.5 6.0
--
-55_C to 25_C
-55_C to 25_C
Typical @ 25C, VCC = 5.0 V
0.1
0.26 0.26 0.26
175 100 35 30
160 100 32 27
0.1 0.1 0.1
10
75 27 15 13
10 20 40 50
4
Guaranteed Limit
Guaranteed Limit
v 85_C v 125_C
v 85_C v 125_C
1.0
0.33 0.33 0.33
220 150 44 37
200 150 40 34
180
0.1 0.1 0.1
10
95 32 19 16
10 20 35 45
40
MC54/74HC164A
1.0
0.40 0.40 0.40
260 200 53 45
250 200 48 42
160
110 36 22 19
0.1 0.1 0.1
10
10 20 30 40
MOTOROLA MHz Unit Unit A A pF pF ns ns ns V
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NOTE: Information on typical parametric values can be found in Chapter 2 of the Motorola High-Speed CMOS Data Book (DL129/D).
MOTOROLA
TIMING REQUIREMENTS (Input tr = tf = 6 ns)
MC54/74HC164A
Symbol
trec
tr, tf
tsu
tw
tw
th
Maximum Input Rise and Fall Times (Figure 1)
Minimum Pulse Width, Reset (Figure 2)
Minimum Pulse Width, Clock (Figure 1)
Minimum Recovery Time, Reset Inactive to Clock (Figure 2)
Minimum Hold Time, Clock to A1 or A2 (Figure 3)
Minimum Setup Time, A1 or A2 to Clock (Figure 3)
Parameter
3-4 VCC V 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 2.0 3.0 4.5 6.0 -55_C to 25_C 1000 800 500 400 50 26 12 10 50 26 12 10 25 15 7 5 3 3 3 3 3 3 3 3
Guaranteed Limit
v 85_C v 125_C
High-Speed CMOS Logic Data DL129 -- Rev 6 1000 800 500 400 60 35 15 12 60 35 15 12 35 20 8 6 3 3 3 3 3 3 3 3 1000 800 500 400 75 45 20 15 75 45 20 15 40 25 9 6 3 3 3 3 3 3 3 3 Unit ns ns ns ns ns ns
MC54/74HC164A
PIN DESCRIPTIONS
INPUTS A1, A2 (Pins 1, 2) Serial Data Inputs. Data at these inputs determine the data to be entered into the first stage of the shift register. For a high level to be entered into the shift register, both A1 and A2 inputs must be high, thereby allowing one input to be used as a data-enable input. When only one serial input is used, the other must be connected to VCC. Clock (Pin 8) Shift Register Clock. A positive-going transition on this pin shifts the data at each stage to the next stage. The shift register is completely static, allowing clock rates down to DC in a continuous or intermittent mode. OUTPUTS QA - QH (Pins 3, 4, 5, 6, 10, 11, 12, 13) Parallel Shift Register Outputs. The shifted data is presented at these outputs in true, or noninverted, form. CONTROL INPUT Reset (Pin 9) Active-Low, Asynchronous Reset Input. A low voltage applied to this input resets all internal flip-flops and sets Outputs QA - QH to the low level state.
SWITCHING WAVEFORMS
tr CLOCK 90% 50% 10%
tw
tf VCC GND tPHL 1/fmax tPLH tPHL Q RESET 50%
tw VCC GND
50% trec VCC
Q
90% 50% 10% tTLH tTHL
CLOCK
50% GND
Figure 1.
Figure 2.
TEST POINT VALID VCC A1 OR A2 50% GND tsu CLOCK th VCC 50% GND * Includes all probe and jig capacitance DEVICE UNDER TEST OUTPUT CL*
Figure 3.
Figure 4. Test Circuit
High-Speed CMOS Logic Data DL129 -- Rev 6
3-5
MOTOROLA
MC54/74HC164A
EXPANDED LOGIC DIAGRAM
CLOCK
8
A1 A2
1 2 D R Q D R Q D R Q D R Q D R Q D R Q D R Q D R Q
RESET
9
3 QA
4 QB
5 QC
6 QD
10 QE
11 QF
12 QG
13 QH
TIMING DIAGRAM
CLOCK A1 A2 RESET QA QB QC QD QE QF QG QH
MOTOROLA
3-6
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC164A
OUTLINE DIMENSIONS
J SUFFIX CERAMIC DIP PACKAGE CASE 632-08 ISSUE Y
-A14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: INCH. 3. DIMENSION L TO CENTER OF LEAD WHEN FORMED PARALLEL. 4. DIMESNION F MAY NARROW TO 0.76 (0.030) WHERE THE LEAD ENTERS THE CERAMIC BODY. INCHES MIN MAX 0.750 0.785 0.245 0.280 0.155 0.200 0.015 0.020 0.055 0.065 0.100 BSC 0.008 0.015 0.125 0.170 0.300 BSC 0 15 0.020 0.040 MILLIMETERS MIN MAX 19.05 19.94 7.11 6.23 5.08 3.94 0.50 0.39 1.65 1.40 2.54 BSC 0.38 0.21 4.31 3.18 7.62 BSC 15 0 0.51 1.01
-B1 7
C
L
-TSEATING PLANE
K F G D 14 PL 0.25 (0.010) N
M
M
S
TA
J 14 PL 0.25 (0.010)
M
T
B
S
DIM A B C D F G J K L M N
N SUFFIX PLASTIC DIP PACKAGE CASE 646-06 ISSUE L
14 8 NOTES: 1. LEADS WITHIN 0.13 (0.005) RADIUS OF TRUE POSITION AT SEATING PLANE AT MAXIMUM MATERIAL CONDITION. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. 4. ROUNDED CORNERS OPTIONAL. DIM A B C D F G H J K L M N INCHES MIN MAX 0.715 0.770 0.240 0.260 0.145 0.185 0.015 0.021 0.040 0.070 0.100 BSC 0.052 0.095 0.008 0.015 0.115 0.135 0.300 BSC 0_ 10_ 0.015 0.039 MILLIMETERS MIN MAX 18.16 19.56 6.10 6.60 3.69 4.69 0.38 0.53 1.02 1.78 2.54 BSC 1.32 2.41 0.20 0.38 2.92 3.43 7.62 BSC 0_ 10_ 0.39 1.01
B
1 7
A F C N H G D
SEATING PLANE
L
J K M
High-Speed CMOS Logic Data DL129 -- Rev 6
3-7
MOTOROLA
MC54/74HC164A
OUTLINE DIMENSIONS
D SUFFIX PLASTIC SOIC PACKAGE CASE 751A-03 ISSUE F
-A-
14 8 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.127 (0.005) TOTAL IN EXCESS OF THE D DIMENSION AT MAXIMUM MATERIAL CONDITION.
-B-
1 7
P 7 PL
0.25 (0.010)
M
B
M
G C
R X 45
F
SEATING PLANE
D
14 PL
K
M
M B
S
J
0.25 (0.010)
T
A
S
DIM A B C D F G J K M P R
MILLIMETERS MIN MAX 8.75 8.55 4.00 3.80 1.75 1.35 0.49 0.35 1.25 0.40 1.27 BSC 0.25 0.19 0.25 0.10 7 0 5.80 6.20 0.25 0.50
INCHES MIN MAX 0.337 0.344 0.150 0.157 0.054 0.068 0.014 0.019 0.016 0.049 0.050 BSC 0.008 0.009 0.004 0.009 7 0 0.228 0.244 0.010 0.019
DT SUFFIX PLASTIC TSSOP PACKAGE CASE 948G-01 ISSUE O
14X K REF NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. DIM A B C D F G H J J1 K K1 L M MILLIMETERS MIN MAX 4.90 5.10 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.50 0.60 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.193 0.200 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.020 0.024 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_
0.10 (0.004) 0.15 (0.006) T U
S
M
TU
S
V
S
N
2X
L/2
14
8
0.25 (0.010) M
L
PIN 1 IDENT. 1 7
B -U-
N F DETAIL E
0.15 (0.006) T U
S
A -V- J J1
SECTION N-N -W-
C 0.10 (0.004) -T- SEATING
PLANE
D
G
H
DETAIL E
MOTOROLA
3-8
EEE CCC EEE CCC EEE CCC EEE CCC
K K1
High-Speed CMOS Logic Data DL129 -- Rev 6
MC54/74HC164A
Motorola reserves the right to make changes without further notice to any products herein. Motorola makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Motorola assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters can and do vary in different applications. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Motorola does not convey any license under its patent rights nor the rights of others. Motorola products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur. Should Buyer purchase or use Motorola products for any such unintended or unauthorized application, Buyer shall indemnify and hold Motorola and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part. Motorola and are registered trademarks of Motorola, Inc. Motorola, Inc. is an Equal Opportunity/Affirmative Action Employer.
How to reach us: USA/EUROPE: Motorola Literature Distribution; P.O. Box 20912; Phoenix, Arizona 85036. 1-800-441-2447 MFAX: RMFAX0@email.sps.mot.com -TOUCHTONE (602) 244-6609 INTERNET: http://Design-NET.com
JAPAN: Nippon Motorola Ltd.; Tatsumi-SPD-JLDC, Toshikatsu Otsuki, 6F Seibu-Butsuryu-Center, 3-14-2 Tatsumi Koto-Ku, Tokyo 135, Japan. 03-3521-8315 HONG KONG: Motorola Semiconductors H.K. Ltd.; 8B Tai Ping Industrial Park, 51 Ting Kok Road, Tai Po, N.T., Hong Kong. 852-26629298
High-Speed CMOS Logic Data DL129 -- Rev 6
CODELINE
3-9
*MC54/74HC164A/D*
MC54/74HC164A/D MOTOROLA

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